The present disclosure relates to a semiconductor device, and more specifically, a fin field effect transistor employing self-aligned source/drain regions and a method manufacturing the same.
Fin field effect transistors are employed in advanced semiconductor circuits to provide a higher on-current density and enhanced gate control over conventional planar field effect transistors. Typical fin field effect transistors employ raised source/drain regions formed by selective epitaxy. A selective epitaxy process requires simultaneous or alternate flow of reactants and etchants at a well controlled temperature. For this reason, process uniformity of a selective epitaxy process is difficult to maintain with a wafer, and wafer to wafer, during a manufacturing process. Thus, a fin field effect transistor is desired that does not require use of a selective epitaxy process for formation of source/drain regions.